As semiconductor devices continue to scale to smaller dimensions, the ability to pattern features becomes increasingly difficult. Present day photolithography tools may employ 193 nm wavelength light to pattern semiconductor devices, where the devices may have dimensions as small as 10 nm to 30 nm.
In addition to challenges for patterning relatively simpler shapes, such as lines, rectangular pads, circles, and the like, the ability to pattern complex structures faces more challenges. Due to optics limitations such as diffraction, etc., patterning features with well-defined edges and especially corners is difficult. For this reason many of the smallest patterns in present day technology are restricted to 1-dimension, i.e., lines and spaces, where such features run just along one direction. These features may be connected as designed using additional layer(s) located above the first layer, which additional layer may have lines and spaces running along a different direction. While this approach enables smaller patterns, the approach also limits the flexibility for circuit design.
In other examples, known features for forming electrical connection between two offset regions within a single device layer include an “L” shape, or a staggered shape, or other 2-dimensional shape. The capability for printing such shapes using conventional lithographic techniques is limited. Even advanced optical proximity correction (OPC) techniques for optical lithography may not adequately print such shapes. In one instance, a staggered structure designed to have straight edges may instead have a rounded shape after lithographic processing. This rounding may result in the generation of a smaller area than the original design for other features to land on, and may additionally cause overlay margin errors where subsequently deposited material, such as a metal feature, overlaps in an unwanted fashion with another metal feature. This rounding is especially prevalent when the dimensions of the pattern are approximately 20 nm or less.
Accordingly, while the ability to generate small 2-dimensional patterns provides greater design flexibility, processes to accomplish this patterning are lacking, especially for defining patterned features below 50 nm in size.
With respect to these and other considerations the present disclosure is provided.